Multistage clock delay circuit and method

Details Multistage clock delay circuit and method Multistage clock delay circuit and method

2005-08-09

2005-08-09

Du, Thuan (Department: 2116)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

Using delay

C713S503000, C327S100000, C327S242000

Reexamination Certificate

active

06928572

ABSTRACT:
A clock delay circuit has a plurality of outputs to provide a sequence of clock signals that togther constitute a multistage clock. The circuit further has a delay adjustment input to adjust the timing of the clock signals for at least one of the outputs relative to the clock signals at another of the outputs. In an embodiment, the circuit has a plurality of these delay adjustment inputs. In a further embodiment, the circuit has a plurality of buffer components to delay the clock signals.

REFERENCES:
patent: 3921079 (1975-11-01), Heffner et al.
patent: 5694062 (1997-12-01), Welch et al.
patent: 6119242 (2000-09-01), Harrison
patent: 6208907 (2001-03-01), Durham et al.
patent: 6731683 (2004-05-01), Fiedler et al.
Yee et al, “Clock-Delayed Domino for Dynamic Circuit Design”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 8, No. 4, Aug. 2000, pp 425-430.
Yee et al, “Clock-Delayed Domino for Adder and Combinational Logic Design”, IEEE, 1063-6404/96, pp 332-337, 1996.
Jung, Perepelitsa, Sobelman, “Time Borrowing in High-Speed Functional Units Using Skew-Tolerant Domino Circuits,” Proceedings, IEEE International Symposium on Circuits and Systems, pp. V-641-V-644, 2000.
Presentation by Carl Sechen dated Mar. 17, 2000.
Taub,Digital Circuits and Microprocessors,pp. 205-212, McGraw-Hill, 1982.

Affiliated with

Also associated with

Rating

Multistage clock delay circuit and method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multistage clock delay circuit and method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multistage clock delay circuit and method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3523831