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Register renaming in which moves are accomplished by swapping re

Electrical computers and digital processing systems: processing – Processing architecture – Superscalar
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Register renaming in which moves are accomplished by...

Electrical computers and digital processing systems: processing – Processing architecture – Superscalar
Reexamination Certificate

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Register renaming system

Electrical computers and digital processing systems: processing – Processing architecture – Superscalar
Reexamination Certificate

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Register renaming to optimize identical register values

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Scoreboarding – reservation station – or aliasing
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Register renaming to reduce bypass and increase apparent...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Commitment control or register bypass
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Register renaming with a pool of physical registers

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Scoreboarding – reservation station – or aliasing
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Register rotation prediction and precomputation

Electrical computers and digital processing systems: processing – Processing control – Arithmetic operation instruction processing
Reexamination Certificate

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Register scoreboard logic with register read availability signal

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Scoreboarding – reservation station – or aliasing
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Register scoreboarding to support overlapped execution of...

Electrical computers and digital processing systems: processing – Processing architecture – Vector processor
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Register set extension for compressed instruction set

Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate variable length...
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Register set used in multithreaded parallel processor...

Electrical computers and digital processing systems: processing – Processing control – Context preserving (e.g. – context swapping – checkpointing,...
Reexamination Certificate

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Register set used in multithreaded parallel processor...

Electrical computers and digital processing systems: processing – Processing control – Context preserving (e.g. – context swapping – checkpointing,...
Reexamination Certificate

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Register transfer unit for electronic processor

Electrical computers and digital processing systems: processing – Processing control – Processing control for data transfer
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Register window fill technique for retirement window having...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Commitment control or register bypass
Reexamination Certificate

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Register window flattening logic for dependency checking...

Electrical computers and digital processing systems: processing – Processing control
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Register window management using first pipeline to change...

Electrical computers and digital processing systems: processing – Processing control
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Register window spill technique for retirement window having...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Commitment control or register bypass
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Register window system and method that stores the next...

Electrical computers and digital processing systems: processing – Processing control
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Registers for 2-D matrix processing

Electrical computers and digital processing systems: processing – Processing architecture – Array processor
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Reissue logic for individually reissuing instructions trapped in

Electrical computers and digital processing systems: processing – Instruction issuing
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