Register renaming system

Details Register renaming system Register renaming system

2007-01-30

2007-01-30

Coleman, Eric (Department: 2183)

Electrical computers and digital processing systems: processing

Processing architecture

Superscalar

C712S216000

Reexamination Certificate

active

10069987

ABSTRACT:
A register renaming system for a processor based on superscalar architecture that can process a larger number of instructions per cycle by providing a free list to hold unallocated physical-register numbers and a mapping table whose entries are provided in respective correspondence with the logical registers and each designed to hold a physical-register number, and by pipelining where dependency checks among instructions are to be done as a pre-process.

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Glenn Reinman etal., Classifying Load and Store Instructions for Memory Renaming, Proceedings of the 13thInternational conference on Supercomputing, May 1999, ACM Press pp. 399-407.
Mayan Moudgill etal., Register Renaming and Dynamic Speculation: an Alternative Approach, 1993 IEEE, pp. 202-213.

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