Counting instructions to skip in superscaler processor
Counting latencies of an instruction table flush, refill and...
Coupling a general purpose processor to an application...
Coupling data in a parallel processing environment
Coupling GP processor with reserved instruction interface...
Cover instruction and asynchronous backing store switch
CPU life-extension apparatus and method
Cross-chip communication mechanism in distributed node...
Cumulative lookahead to eliminate chained dependencies
Cumulative lookahead to eliminate chained dependencies
Custom code processing in PGA by providing instructions from...
Customizable instruction set processor with non-configurable/con
Cycle count replication in a simultaneous and redundantly...
Cycle segmented prefix circuits