Coupling data in a parallel processing environment

Details Coupling data in a parallel processing environment Coupling data in a parallel processing environment

2006-04-14

2009-12-22

Chan, Eddie P (Department: 2183)

Electrical computers and digital processing systems: processing

Processing architecture

Array processor

C712S010000, C712S014000, C712S016000, C712S018000, C712S019000

Reexamination Certificate

active

07636835

ABSTRACT:
An integrated circuit comprises a plurality of tiles. Each tile comprises a processor, and a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received from the processor to switches of other tiles. The integrated circuit further comprises one or more interface modules including circuitry to transfer data to and from a device external to the tiles; and a sub-port routing network including circuitry to route data between a port of a switch and a plurality of sub-ports coupled to one or more interface modules.

REFERENCES:
patent: 5717943 (1998-02-01), Barker et al.
patent: 5859981 (1999-01-01), Levin et al.
patent: 5892962 (1999-04-01), Cloutier
patent: 5898881 (1999-04-01), Miura et al.
patent: 6009531 (1999-12-01), Selvidge et al.
patent: 6145072 (2000-11-01), Shams et al.
patent: 6185667 (2001-02-01), Abercrombie et al.
patent: 6467009 (2002-10-01), Winegarden et al.
patent: 6526461 (2003-02-01), Cliff
patent: 6728841 (2004-04-01), Keller
patent: 6738891 (2004-05-01), Fujii et al.
patent: 6751721 (2004-06-01), Webb et al.
patent: 6859869 (2005-02-01), Vorbach
patent: 6961782 (2005-11-01), Denneau et al.
patent: 7394288 (2008-07-01), Agarwal
patent: 7461236 (2008-12-01), Wentzlaff
patent: 2002/1004989 (2002-04-01), Williams et al.
patent: 2002/0184529 (2002-12-01), Foster et al.
patent: 2002/1019891 (2002-12-01), Blomgren et al.
patent: 2004/0103264 (2004-05-01), Fujii et al.
patent: 2004/0250046 (2004-12-01), Gonzalez et al.
patent: 2004/0268286 (2004-12-01), New et al.
patent: 2005/0021699 (2005-01-01), Kota et al.
patent: 2005/0160253 (2005-07-01), Lescure
patent: 2006/0179429 (2006-08-01), Eggers et al.
patent: 2006/0241878 (2006-10-01), Jung et al.
patent: WO 2004/072796 (2004-08-01), None
Agarwal, Anant. “Raw Computation,”Scientific Americanvol. 281, No. 2:44-47, Aug. 1999.
Taylor, Michael Bedford et. al., “Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams,”Proceedings of International Symposium on Computer Architecture, Jun. 2004.
Taylor, Michael Bedford et. al., “Scalar Operand Networks: On-Chip Interconnect for ILP in Partitioned Architectures,”Proceedings of the International Symposium on High Performance Computer Architecture, Feb. 2003.
Taylor, Michael Bedford et. al., “A 16-Issue Multiple-Program-Counter Microprocessor with Point-to-Point Scalar Operand Network,”Proceedings of the IEEE International Solid-State Circuits Conference, Feb. 2003.
Taylor, Michael Bedford et. al., “The Raw Microprocessor: A Computational Fabric for Software Circuits and General-Purpose Programs,”IEEE Micro, pp. 25-35, Mar.-Apr. 2002.
Lee, Walter et. al., “Space-Time Scheduling of Instruction-Level Parallelism on a Raw Machine,”Proceedings of the Eighth International Conference on Architectural Support for Programming Languages and Operating Systems(ASPLOS-VIII), San Jose, CA, Oct. 4-7, 1998.
Kim, Jason Sungtae et. al., “Energy Characterization of a Tiled Architecture Processor with On-Chip Networks,”International Symposium on Low Power Electronics and Design, Seoul, Korea, Aug. 25-27, 2003.
Barua, Rajeev et. al., “Compiler Support for Scalable and Efficient Memory Systems,”IEEE Transactions on Computers, Nov. 2001.
Waingold, Elliot et. al., “Baring it all to Software: Raw Machines,”IEEE Computer, pp. 86-93, Sep. 1997.
Lee, Walter et. al., “Convergent Scheduling,”Proceedings of the 35thInternational Symposium on Microarchitecture, Istanbul, Turkey, Nov. 2002.
Wentzlaff, David and Anant Agarwal, “A Quantitative Comparison of Reconfigurable, Tiled, and Conventional Architectures on Bit-Level Computation,”MIT/LCS Technical Report LCS-TR-944, Apr. 2004.
Suh, Jinwoo et. al., “A Performance Analysis of PIM, Stream Processing, and Tiled Processing on Memory-Intensive Signal Processing Kernels,”Proceedings of the International Symposium on Computer Architecture, Jun. 2003.
Barna, Rajeev et. al., “Maps: A Compiler-Managed Memory System for Raw Machines,”Proceedings of the Twenty-Sixth International Symposium on Computer Architecture(ISCA-26), Atlanta, GA, Jun. 1999.
Barua, Rajeev et. al., “Memory Bank Disambiguation using Modulo Unrolling for Raw Machines,”Proceedings of the Fifth International Conference on High Performance Computing, Chennai, India, Dec. 17-20, 1998.
Agarwal, A. et. al., “The Raw Compiler Project,”Proceedings of the Second SUIF Compiler Workshop, Stanford, CA, Aug. 21-23, 1997.
Taylor, Michael Bedford et. al., “Scalar Operand Networks,”IEEE Transactions on Parallel and Distributed Systems(Special Issue on On-Chip Networks), Feb. 2005.
Taylor, Michael. The Raw Prototype Design Document V5.01 [online]. Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Sep. 6, 2004 [retrieved on Sep. 25, 2006]. Retrieved from the Internet: <ftp://ftp.cag.lcs.mit.edu/pub/raw/documents/RawSpec99.pdf>.
Moritz, Csaba Andras et. al., “Hot Pages: Software Caching for Raw Microprocessors,”MIT/LCS Technical Memo LCS-TM-599, Aug. 1999.
USPTO Non-Final Office Action in U.S. Appl. No. 11/404,187, mailed Feb. 5, 2009, 15 pages.
USPTO Non-Final Office Action in U.S. Appl. No. 11/404,655, mailed Mar. 23, 2009, 14 pages.
USPTO Non-Final Office Action in U.S. Appl. No. 11/404,207, mailed Nov. 13, 2008, 9 pages.
USPTO Non-Final Office Action in U.S. Appl. No. 11/302,961, mailed Feb. 9, 2009, 12 pages.
USPTO Non-Final Office Action in U.S. Appl. No. 12/130,462, mailed Mar. 3, 2009, 8 pages.
Fish & Richardson P.C., Application for United States Letters Patent (unpublished) in U.S. Appl. No. 11/302,961, filed Dec. 13, 2005, 64 pages.

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