Cross-chip communication mechanism in distributed node...

Details Cross-chip communication mechanism in distributed node... Cross-chip communication mechanism in distributed node...

2003-04-28

2009-08-11

Patel, Niketa I (Department: 2181)

Electrical computers and digital processing systems: processing

Processing architecture

Array processor

C361S695000, C361S689000, C361S633000, C712S012000

Reexamination Certificate

active

07574581

ABSTRACT:
A method of communicating between processing units on different integrated circuit chips in a multi-processor computer system by issuing a command from a source processing unit to a destination processing unit, receiving the command at the destination processing unit while the destination processing unit is processing program instructions, and accessing free-running, scan registers in clock-controlled components of the destination processing unit without interrupting processing of the program instructions by the destination processing unit. The access may be a read from status or mode registers of the destination processing unit, or write to control or mode registers. Many processing units can be interconnected in a ring topology, and the access command can be passed from the source processing unit through several other processing units before reaching the destination processing unit.

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