Pipelined processor executing logical or mathematical...
Pipelined processor method and circuit with interleaving of...
Pipelined two-cycle branch target address cache
Pre-prefetching target of following branch instruction based...
Precise counter hardware for microcode loops
Precoding branch instructions to reduce branch-penalty in...
Predecode buffer including buffer pointer indicating another...
Predecoding multiple instructions as one combined...
Predicate controlled software pipelined loop processing with...
Predicted return address from return stack entry designated...
Predicted return address from return stack entry designated...
Predicted return address selection upon matching target in...
Predicting a jump target based on a program counter and...
Predicting for all branch instructions in a bunch based on histo
Predicting instruction branches with a plurality of global...
Predictors with adaptive prediction threshold
Prefetch buffer which stores a pointer indicating an initial pre
Prefetching exception vectors by early lookup exception...
Prefetching instructions in mis-predicted path for low...
Prefetching using future branch path information derived...