Predicted return address from return stack entry designated...

Details Predicted return address from return stack entry designated... Predicted return address from return stack entry designated...

2005-08-22

2008-03-25

Kim, Kenneth S. (Department: 2111)

Electrical computers and digital processing systems: processing

Processing control

Branching

C712S240000

Reexamination Certificate

active

07350062

ABSTRACT:
An information processing apparatus is capable of speculatively performing an execution, such as a pipeline/superscalar/out-of-order execution and equipped with a branch prediction mechanism (a branch history). The information processing apparatus, in order to process an instruction sequence that includes a subroutine at a high speed, is further equipped with a return address stack, of which the stack operation is activated at a time of completing execution of an subroutine call/return correspondent instruction and an entry designating unit (pointer), in order to adjust a time difference resulting from an instruction fetch being executed prior to completing an instruction, pointing to a position relative to the stack front and adjusting a time difference between an instruction fetch performed speculatively in advance and completion of an instruction both at a time of completing execution of a branch instruction that is correspondent to a subroutine call/return and at a time of predicting a subroutine call/return in synchrony to the instruction fetch. An entry position correspondent to a stack position pointed to by the entry designation unit is adopted as a subroutine call/return prediction address and consequently the prediction of the subroutine return address becomes more accurate and the processing speed becomes higher.

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