Electrical computers and digital processing systems: processing – Processing control – Branching
Reexamination Certificate
2007-04-17
2007-04-17
Chan, Eddie (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Branching
C712S219000, C712S221000, C708S523000
Reexamination Certificate
active
10299412
ABSTRACT:
A method of executing an instruction stream in a pipelined execution unit of depth, p, comprises loading the instruction stream; detecting an iteration of an instruction in the loaded instruction stream; interleaving p steams of instances of the instruction in the pipeline; detecting an end of the iteration; and combining results obtained from the p streams after all programmed iterations have completed. A computational circuit comprises a register which can hold a value representing both an operand and result of an iterative operation; a multiplexer having a first input connected to receive the operand from the register, a second input connected to a source of an identify value for the iterative operation, and an output; and an operator circuit having an input connected to receive a value from the multiplexer output, and an output connected to return thee result to the register. A method of executing an instruction stream in a pipelined execution unit comprises providing to the execution unit the instruction stream as a sequence of instruction in natural order absent software scheduling; detecting an iteration of an instruction in the sequence of instruction; and introducing into a pipeline of the pipelined execution unit plural instances of the iterated instruction, each with different data. A method of executing an instruction stream in a pipelined execution unit comprises detecting an iteration of an instruction in the instruction stream; independently executing plural streams of the iterated instruction; and recombining the independently executed plural streams to provide a single result; wherein independently executing and recombining use not more than one destination register and not more than one temporary register. In a programmable data processor including instruction interlocks and including a pipelined computation unit having a pipeline of depth p, a circuit comprises a controller constructed and arranged to detect an iterative computation in an incoming instruction stream.
REFERENCES:
patent: 4853890 (1989-08-01), Abe et al.
patent: 5123108 (1992-06-01), Olson et al.
patent: 2002/0194466 (2002-12-01), Catherwood et al.
patent: 2003/0154227 (2003-08-01), Howard et al.
patent: 0 718 757 (1996-06-01), None
patent: WO 02/077794 (2002-10-01), None
Hennessy and Patterson, Computer Organization and Design, Morgan Kaufman Publishers, Inc., 1998, pp. 378, B-9 and Last Page (un-numbered).
The Authoritative Dictionary of IEEE Standards Terms, 7th Ed., IEEE Press, 2000, p. 716.
Analog Devices Inc.
Chan Eddie
Fiegle Ryan
Wolf Greenfield & Sacks P.C.
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