Central processing unit with integrated graphics functions

Central processing unit with integrated graphics functions

Circuit and method for reducing data dependencies between instru

Circuit and method for selectively stalling interrupt...

Circuit arrangement for profiling a programmable processor...

Circuit for loading a memory rules for a fuzzy logic microproces

Circuit for time-sharing of configurable I/O pins

Circuits, system, and methods for processing multiple data strea

Clustered architecture in a VLIW processor

Coarse-grained look-up table architecture

Code segment default operation determination

Collation of interrupt control devices

Combined associative processor and random access memory...

Combined Instruction and address caching system using...

Combining hardware and software to provide an improved microproc

Combining results of selectively executed remaining...

Communication link control among inter-coupled multiple...

Communication link control among inter-coupled multiple...

Communication paths for enabling inter-sequencer...

Communication system for controlling intercommunication...