Communication paths for enabling inter-sequencer...

Electrical computers and digital processing systems: processing – Processing architecture – Distributed processing system

Reexamination Certificate

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C710S016000, C710S305000

Reexamination Certificate

active

07904696

ABSTRACT:
In one embodiment, the present invention includes a method for communicating an assertion signal from a first instruction sequencer to a plurality of accelerators coupled to the first instruction sequencer via a dedicated interconnect, detecting the assertion signal in the accelerators and communicating a request for a lock on a second interconnect coupled to the first instruction sequencer and the accelerators, and registering an accelerator that achieves the lock by communication of a registration message for the accelerator to the first instruction sequencer via the second interconnect. Other embodiments are described and claimed.

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U.S. Appl. No. 11/477,643, filed Jun. 29, 2006 entitled, “Handling Address Translations and Exceptions of a Heterogeneous Resource,” by Hong Wang, et al.

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