Circuit and method for reducing data dependencies between instru

Details Circuit and method for reducing data dependencies between instru Circuit and method for reducing data dependencies between instru

1998-10-05

2000-12-05

Eng, David Y.

Electrical computers and digital processing systems: processing

Processing architecture

Data driven or demand driven processor

G06F 928

Patent

active

061579955

ABSTRACT:
A circuit and method is disclosed which reduces data dependencies between instructions within an application program thereby reducing time delays associated therewith. In one embodiment, a data dependent instruction is translated into at least first and second speculative data independent instructions wherein the data dependent instruction, if executed, produces results which are dependent on a data result provided by execution of a data independent instruction. The first and second speculative data independent instructions are executed to generate first and second speculative results. It is noted that these results are generated independent of the results produced by executing the data independent instruction. Once the data independent instruction is executed and its data result is generated, one of the first and second speculative results is invalidated depending on the value of the data results.

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Johnson of Advanced Micro Devices, Inc., "Superscalar Microprocessor Design," PTR Prentice Hall, Inc., 1991, pp. 69-71.
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Halfhill, "Beyond Pentium ll," BYTE Magazine-Dec. 1997, downloaded and printed from www.byte.com on Oct. 5, 1998, 9 pages.
Lee, "Branch Prediction Strategies and Branch Target Buffer Design, " Computer, Jan. 1984, pp. 6-22.

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