Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...
Reexamination Certificate
1993-08-27
2001-03-20
Ellis, Richard L. (Department: 2783)
Electrical computers and digital processing systems: processing
Processing architecture
Microprocessor or multichip or multimodule processor having...
C710S035000
Reexamination Certificate
active
06205536
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a data processor and a microprocessor therefor which make it possible to efficiently access a memory using a high-speed bus protocol.
2. Description of Related Art
As the performance of data processors has increased, the width of microprocessor data buses in data processors connecting to memories has gradually extended from four bits to eight bits, then to 16 bits and 32 bits. In a data processor, the speed of processing instructions and data greatly affects the data processor's performance.
For example, in order to process data in a memory-to-register operation in one clock cycle, the memory data and instruction need to be read in one clock cycle. One solution that has been developed is a processor with a separate data bus for accessing data operands and an instruction bus for accessing instruction codes.
A data processor providing independent data and instruction buses, is known in the art. For example, the “AM29000” made by Advanced Micro Devices, Inc. or the “CLIPPER” made by Fairchild Semiconductor, are such processors. These data processors are described in detail in the “AM29000 User's Manual” (Advanced Micro Devices, Inc., 1987) or “CLIPPER Module Product Description” (Fairchild Semiconductor, 1985).
The AM29000 has a 32-bit instruction bus, a 32-bit data bus and a 32-bit address bus. To access an instruction, the processor outputs an instruction address onto the address bus, and inputs the instruction from the instruction bus. To access data, the processor outputs a data address onto the address bus, and inputs/outputs data through the data bus. A burst transfer mode which accesses consecutive instructions or data locations in response to one address on the address bus is also supported.
The “CLIPPER” has a multiplexed, 32-bit instruction address bus which handles instruction addresses and instructions and a multiplexed, 32-bit data address bus which handles data addresses and data.
The so-called address pipelining method has also been developed to speed transferring instructions and data, while keeping the memory access time constant, by outputting the address in advance of a memory access cycle. An example of address pipelining is provided by the “i80386” made by Intel Corporation, and this function is described in detail in the publication “80386 High Performance Microprocessor With Integrated Memory Management” (Intel Corporation, 1985).
FIG. 1
shows a conventional data processor, which comprises a CPU
71
, an instruction address bus
81
, an instruction bus
82
, a data address bus
84
and a data bus
85
, wherein an instruction cache
72
and a data cache
73
independently execute an instruction access and a data access, respectively.
CPU
71
accesses instruction cache
72
by sending/receiving control signals through an instruction control bus
83
and using instruction address bus
81
and instruction bus
82
. Also, CPU
71
accesses data cache
73
by sending/receiving control signals through a data control bus
86
and using data address bus
84
and data bus
85
. When a cache miss occurs, CPU
71
sends and receives control signals through to a memory control bus
88
and using a memory address bus
87
and a memory data bus
89
causes instruction cache
72
or data cache
73
to access a main memory
74
.
As described above, various attempts have been made to improve the transferring ability of the bus in the conventional data processor. However, an increase in the number of bits or an increase in the number of buses incurs an increase in the number of pins, and thereby increasing the cost of the microprocessor, the data processor using the microprocessor, and the system incorporating the data processor. Although the transfer speed of the bus can be increased by increasing the clock rate, an increase in the clock rate will increase the cost of the processor, as faster circuits are needed.
In a data processor using the “AM29000” as a microprocessor, one address bus is used for both instruction access and data access. Therein, instructions and data cannot be simultaneously access. This is true for single accesses, as well as in the burst mode. For this reason, where instructions and data are accessed alternately, one by one, the address output creates a bottleneck despite the fact that the data bus and the instruction bus are independent, and a processor time equal to a sum of the time of instruction access and the time of data access is required.
In the “CLIPPER” data processor, access to instruction codes and access to data are performed by independent buses, and, therefore, both accesses can be performed separately, thus avoiding the problems of the “AM29000”. However, when executing an instruction read or a data read, it is necessary to input the instruction or data immediately after the processor has output the address, and the signal direction on bus must reverse quickly. Accordingly, the circuit design of buses for this system becomes more difficult as the system clock frequency controlling the whole apparatus increases.
In a system having address pipelining, access time to memory can be increased by outputting the address in advance, but the access time needed for one instruction or one data access is not reduced. For this reason, a non-pipeline access mode is needed that does not output the address in advance to improve performance. Consequently, the two modes need to be supported and the system design is complicated.
In the example in
FIG. 1
, the instruction cache
72
and the data cache
73
can be accessed independently, and the CPU
71
can be operated efficiently. However, two address buses for instruction address bus
81
and the data address bus
84
are required, and the number of pins for CPU
71
and the number of pins for the data processor are increased, resulting in increased cost. To reduce address skew by the address bus, all bits must be transferred without a deviation in timing. For this reason, a stable power source and a stable ground potential must be supplied for the address output circuit of the microprocessor, and where the number of address buses increases from one to two, not only do the number of pins increase by the number of bits, but the power source and ground wiring must also be increased at the same time.
SUMMARY OF THE INVENTION
The principal object of the present invention is to provide data processor using a microprocessor as a CPU, the system having an independent data bus and an independent instruction bus, and performing data accesses and instruction accesses efficiently without increasing the number of address bus lines used for output by adopting a configuration where the data address and the instruction address are output by on a single address bus in a time-shared manner.
The data processor and the microprocessor of the present invention comprises 32-bit address bus for transferring instruction and data addresses, a 32-bit instruction bus for transferring instructions and a 64-bit data bus for transferring data. Also, two systems of bus control signals controlling the instruction access cycle and the data access cycle in an independent manner are provided. The two systems of bus access signals include an instruction valid signal showing that the instruction address output to the address bus is valid, a data address valid signal showing that the data address output to the address bus is valid, an instruction transfer end signal indicating the end of an instruction access cycle and a data transfer end signal indicating the end of a data access cycle. Besides these signals, an access type signal is provided which indicates the type of address, either instruction or data, being transferred on the address bus.
In the data processor and the microprocessor of the present invention, data addresses and instruction addresses are transferred using the address bus, data is transferred on the data bus, and instructions are transferred on the instruction bus. The type of the address transferred by the address bus is
Ellis Richard L.
Mitsubishi Denki & Kabushiki Kaisha
Townsend and Townsend / and Crew LLP
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