Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
2011-08-30
2011-08-30
Pan, Daniel (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
C716S117000
Reexamination Certificate
active
08010771
ABSTRACT:
The invention provides a communication system including a plurality of communication nodes respectively arranged at predetermined lattice points in lattice space forming a three-dimensional rectangular solid, a communication link that interconnects communication nodes arranged at adjacent lattice points, and a shortcut link that connects, for at least two faces that are not an end face on the lattice space among faces formed of communication nodes of which any adjacent lattice points do not have communication nodes, a communication node constituting one face and a communication node constituting another face.
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patent: 2005/0177593 (2005-08-01), Solomon
Inagaki Takeshi
Minami Aya
Miwa Yohichi
Cantor & Colburn LLP
International Business Machines - Corporation
Kinnaman, Jr. William A.
Pan Daniel
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