Electrical computers and digital processing systems: processing – Processing architecture – Superscalar
Patent
1996-04-19
1999-08-17
Donaghue, Larry D.
Electrical computers and digital processing systems: processing
Processing architecture
Superscalar
345530, 345502, G06F 1500
Patent
active
059387564
ABSTRACT:
The integer execution unit (IEU) of a central processing unit (CPU) is provided with a graphics status register (GSR) for storing a graphics data scaling factor and a graphics data alignment address offset. Additionally, the CPU is provided with a graphics execution unit (GRU) for executing a number of graphics operations in accordance to the graphics data scaling factor and alignment address offset, the graphics data having a number of graphics data formats. In one embodiment, the GRU is also used to execute a number of graphics data addition, subtraction, rounding, expansion, merge, alignment, multiplication, logical, compare, and pixel distance operations. The graphics data operations are categorized into a first and a second category, and the GRU concurrently executes one graphics operations from each category. Furthermore, under this embodiment, the IEU is also used to execute a number of graphics data edge handling and 3-D array addressing operations, while the load and store unit (LSU) of the CPU is also used to execute a number of graphics data load and store operations, including conditional store operations.
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Kohn Leslie Dean
Van Hook Timothy J.
Yung Robert
Donaghue Larry D.
Sun Microsystems Inc.
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