Apparatus for reducing a computational result to the range bound

Apparatus for the hierarchical and distributed control of...

Apparatus using a multiple instruction register logarithm...

Apparatus, method, system and executable module for...

Apparatus, method, system and executable module for...

Apparatus, method, system and executable module for...

Apparatus, system, and method for determining the...

Application-specific integrated circuit for processing...

Arbiter system for central processing unit having dual...

Architecture for a process complex of an arrayed pipelined...

Architecture for a processor complex of an arrayed pipelined...

Architecture for a processor complex of an arrayed pipelined...

Architecture for a processor complex of an arrayed pipelined...

Area and power efficient VLIW processor with improved speed

Arithmetic processing architecture having a portion of...

Arithmetic units responsive to common control signal to...

Array of Boolean logic controlled processing elements with...

Array of processing elements with local registers

Array synchronization with counters

Array type operation device