Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...
Reexamination Certificate
1998-08-11
2004-04-20
Lin, Wen Tai (Department: 2154)
Electrical computers and digital processing systems: processing
Processing architecture
Microprocessor or multichip or multimodule processor having...
C712S032000, C712S035000, C712S023000
Reexamination Certificate
active
06725355
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a microprocessor and a method thereof.
2. Description of the Related Art
When classifying microprocessors by general design concepts, they can be divided into, for example, a reduced instruction set computer (RISC) type and a complex instruction set computer (CISC) type.
Note that the program execution time, which decides the performance of the microprocessor per se, can be expressed by the following formula (1):
[Formula 1]
Program execution time=number of executed instructions (IC)×average number of clock cycles required per instruction (CPI)×clock cycle time (CCT)(1)
An RISC type microprocessor is based on the design concept of making the CPI in the above formula (1) close to 1 as much as possible by using instruction pipeline processing.
Therefore, in an RISC type microprocessor, instructions are made a fixed single length and a register-register format (load/store type architecture: only source operand for processing instruction is register operand) is used as an instruction format from the viewpoint of simplifying the functions of instructions functions to be suitable for instruction pipeline processing.
Also, an RISC type microprocessor performs static code scheduling by a compiler so as to prevent delays in the instruction pipeline processing.
On the other hand, a CISC type microprocessor is based on the design concept of improving the level of functions of instructions so as to eliminate the IC of the above formula (1).
Accordingly, in a CISC type microprocessor, instructions are made a plurality of fixed lengths or variable lengths, and the instruction format includes a mixture of the register-memory format and memory-memory format (where a memory operand is also possible for a source operand of a processing instruction). Namely, it direct processing between a register and memory is made possible.
When data on a memory is processed by an arithmetic and logic unit (ALU), an RISC type microprocessor requires at least two instructions, a load instruction and a store instruction, for accessing the memory.
On the other hand, a CISC type microprocessor does not require any instruction only for accessing the memory.
In a CISC type memory-processor, a large bit field is required in an instruction for designating a memory address. As mentioned above, a variable length instruction is used in many cases.
However, the decoding circuit tends to become complicated and large in size when using variable length instructions. Therefore, in a CISC type microprocessor, a the program execution time is being shortened by using super scalar technique or out-of-order technique to speed up the processing of data in the memory at the present time.
Below, an explanation will be given of the method of accessing a memory in a conventional RISC type and the CISC type microprocessor.
FIG. 20
is a view for explaining general-purpose registers in conventional RISC type and the CISC type microprocessors.
As shown in
FIG. 20
, a conventional microprocessor is provided with, for example, 16 general-purpose registers. Assume that these 16 general-purpose registers are referred to as r
0
to r
15
.
When these registers are mounted in a processor architecture comprised of a set of 3-operand processing instructions, three ports in total, that is, two read ports and one write port, are necessary
With a 3-operand processing instruction, as shown in
FIG. 21
, it is possible to designate three register designators of an ALU processing instruction.
Note that, in
FIG. 21
, a comment on the instruction written on the left side of the semicolon is given on the right side of the semicolon.
The instruction shown in
FIG. 21
is an instruction to execute “r
2
−r
3
+r
4
”. The registers r
0
to r
15
are general-purpose ones and are used for temporarily holding values.
In a processor using a load/store type architecture, a load/store instruction is executed for a general-purpose register in order to realize a load/store operation on a memory. There are no instructions which are directly entered into the ALU processor. This is often seen in RISC type processors.
As shown in
FIG. 22
, when processing data in the memory, it is necessary to execute a load instruction “
1
w r
3
,
0
(r
10
)” once.
On the other hand, in some CISC processors, it is possible to designate data on a memory as an operand of an ALU processing instruction. In this case, however, a general-purpose register is not used. A memory buffer is used directly.
Below, an explanation will be given of pipeline processing in a conventional RISC type processor.
In an RISC type processor, a five-stage or eight-stage pipeline structure is often used.
For example, the “R3000” (product name) of the MIPS Co., as shown in
FIG. 23
, uses a five-stage pipeline comprising an instruction fetch (IF) stage, an instruction decode (DEC) stage, a memory (MEM) stage, and a write back (WB) stage.
This processor fetches (reads) an instruction in the first IF stage and decodes the instruction in the second DEC stage. Note that if the instruction designates a general-purpose register as a source register, the processor decodes the instruction in the DEC stage, then reads the data from the general-purpose register.
Next, at the third ALU stage, it executes an ALU processing instruction. Note that when the fetched instruction is not an ALU instruction, nothing is done in the ALU stage and the data is output to the ALU output port as it is.
Next, in the fourth MEM stage, when the fetched instruction is a memory access instruction, the processor outputs a memory address used for memory access to a memory unit for accessing the memory.
Next, fifth, for an instruction which designates a general-purpose register as a destination register, the processor writes back the result of the ALU processing in the general-purpose register. If the instruction is a memory read instruction (load instruction), it receives a value from the memory unit and writes it in the general-purpose register.
As shown in
FIG. 23
, a processor using a five-stage pipeline performs, for example, in a clock cycle X, the WB stage of a code C
1
, the MEM stage of a code C
2
, the ALU stage of a code C
3
, the DEC stage of ta code C
4
, and the IF stage of a code C
5
by multiplexing.
However, as explained above, since an RISC type processor uses a load/store type instruction set architecture, the ALU processing instructions and the load/store instructions exist separately and independently of each other.
Accordingly, in order to multiplex the desired instruction with these instructions, for example, use of the five-stage pipeline structure shown in
FIG. 23
is convenient. Namely, the memory access instruction and other instructions can be executed simultaneously. Since it is assumed that there is only one system (1 set) of paths for memory access, it is impossible to execute memory read and memory write operations at the same MEM stage simultaneously.
Also, when treating a memory access instruction and the other instructions as independent, unused pipeline stages end up occurring. For example, in a transfer instruction between registers, the function of the MEM stage is not used. Also, in a memory access instruction, the function of the ALU stage is not used. Note that the address generating processing for memory access is performed in units other than the ALU.
In the five-stage pipeline processing shown in
FIG. 23
, when data on the memory is processed by the ALU, the program is written, for example, as shown in
FIG. 24
In the program shown in
FIG. 24
, first, the processor loads the data at the memory address indicated by the register r
10
to the register r
2
by the instruction “
1
w r
2
,
0
(r
10
)”. Next, it adds the values in the registers r
2
and r
9
and inserts the result in the register r
3
by the instruction “addu r
3
, r
2
, r
9
”. Next, it stores (writes back) the value in the register r
3
in the memory address indicated by the register r
11
by the instruction “s
Kananen Ronald P.
Lin Wen Tai
Rader & Fishman & Grauer, PLLC
LandOfFree
Arithmetic processing architecture having a portion of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Arithmetic processing architecture having a portion of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Arithmetic processing architecture having a portion of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3195118