Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
2005-08-02
2009-10-20
Treat, William M (Department: 2181)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
Reexamination Certificate
active
07606996
ABSTRACT:
An array calculation device that includes a processor array composed of a plurality of processor elements having been assigned with orders, acquires an instruction in each cycle, generates, in each cycle, operation control information for controlling an operation of a processor element of a first order, and then generates an instruction to the processor element of the first order in accordance with the operation control information and the acquired instruction, and also generates, in each cycle, operation control information for controlling an operation of each processor element of a next order and onwards, in accordance with operation control information generated for controlling an operation of a processor element of an immediately preceding order, and then generates an instruction to each processor element of the next order and onwards, in accordance with the operation control information generated and the acquired instruction.
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Maeda Masaki
Morishita Hiroyuki
Tanaka Takeshi
Wakayama Yorihiko
Panasonic Corporation
Treat William M
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