Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
2008-01-15
2008-01-15
Treat, William M. (Department: 2181)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
Reexamination Certificate
active
07320062
ABSTRACT:
The present invention concerns configuration of a new category of integrated circuitry for adaptive computing. The various embodiments provide an executable information module for an adaptive computing engine (ACE) integrated circuit and may include configuration information, operand data, and may also include routing and power control information. The ACE IC comprises a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative to configure the plurality of heterogeneous computational elements for a plurality of different functional modes.
REFERENCES:
patent: 6986021 (2006-01-01), Master et al.
Master Paul L.
Smith Stephen J.
Watson John
Kaufman Marc S.
Nixon & Peabody LLP
QST Holdings LLC
Treat William M.
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