Architecture for a processor complex of an arrayed pipelined...

Details Architecture for a processor complex of an arrayed pipelined... Architecture for a processor complex of an arrayed pipelined...

2008-05-27

2008-05-27

Donaghue, Larry D. (Department: 2154)

Electrical computers and digital processing systems: processing

Processing architecture

Array processor

C710S052000

Reexamination Certificate

active

11023283

ABSTRACT:
A processor complex architecture facilitates accurate passing of transient data among processor complex stages of a pipelined processing engine. The processor complex comprises a central processing unit (CPU) coupled to an instruction memory and a pair of context data memory structures via a memory manager circuit. The context memories store transient “context” data for processing by the CPU in accordance with instructions stored in the instruction memory. The architecture further comprises data mover circuitry that cooperates with the context memories and memory manager to provide a technique for efficiently passing data among the stages in a manner that maintains data coherency in the processing engine. An aspect of the architecture is the ability of the CPU to operate on the transient data substantially simultaneously with the passing of that data by the data mover.

REFERENCES:
patent: 4590554 (1986-05-01), Glazer et al.
patent: 4773038 (1988-09-01), Hillis et al.
patent: 4791641 (1988-12-01), Hillis
patent: 4805091 (1989-02-01), Thiel et al.
patent: 4809202 (1989-02-01), Wolfram
patent: 4862392 (1989-08-01), Steiner
patent: 4870568 (1989-09-01), Kahle et al.
patent: 4922486 (1990-05-01), Lidinsky et al.
patent: 4965717 (1990-10-01), Cutts, Jr. et al.
patent: 4993028 (1991-02-01), Hillis
patent: 5070446 (1991-12-01), Salem
patent: 5093801 (1992-03-01), White et al.
patent: 5111198 (1992-05-01), Kuszmaul
patent: 5113510 (1992-05-01), Hillis
patent: 5117420 (1992-05-01), Hillis et al.
patent: 5129077 (1992-07-01), Hillis
patent: 5148547 (1992-09-01), Kahle et al.
patent: 5151996 (1992-09-01), Hillis
patent: 5157663 (1992-10-01), Major et al.
patent: 5175865 (1992-12-01), Hillis
patent: 5212773 (1993-05-01), Hillis
patent: 5222216 (1993-06-01), Parish et al.
patent: 5222237 (1993-06-01), Hillis
patent: 5247613 (1993-09-01), Bromley
patent: 5247694 (1993-09-01), Dahl
patent: 5255291 (1993-10-01), Holden et al.
patent: 5261105 (1993-11-01), Potter et al.
patent: 5265207 (1993-11-01), Zak et al.
patent: 5274631 (1993-12-01), Bhardwaj
patent: 5289156 (1994-02-01), Ganmukhi
patent: 5295258 (1994-03-01), Jewett et al.
patent: 5301310 (1994-04-01), Isman et al.
patent: 5317726 (1994-05-01), Horst
patent: 5355492 (1994-10-01), Frankel et al.
patent: 5357612 (1994-10-01), Alaiwan
patent: 5361363 (1994-11-01), Wells et al.
patent: 5367692 (1994-11-01), Edelman
patent: 5388214 (1995-02-01), Leiserson et al.
patent: 5388262 (1995-02-01), Hillis
patent: 5390298 (1995-02-01), Kuszmaul et al.
patent: 5404296 (1995-04-01), Moorhead
patent: 5404562 (1995-04-01), Heller et al.
patent: 5410723 (1995-04-01), Schmidt et al.
patent: 5455932 (1995-10-01), Major et al.
patent: 5485627 (1996-01-01), Hillis
patent: 5530809 (1996-06-01), Douglas et al.
patent: 5535408 (1996-07-01), Hillis
patent: 5561669 (1996-10-01), Lenney et al.
patent: 5617538 (1997-04-01), Heller
patent: 5621885 (1997-04-01), Del Vigna, Jr.
patent: 5627965 (1997-05-01), Liddell et al.
patent: 5673423 (1997-09-01), Hillis
patent: 5686960 (1997-11-01), Sussman et al.
patent: 5710814 (1998-01-01), Klemba et al.
patent: 5742604 (1998-04-01), Edsall et al.
patent: 5751955 (1998-05-01), Sonnier et al.
patent: 5764636 (1998-06-01), Edsall
patent: 5787255 (1998-07-01), Parlan et al.
patent: 5822608 (1998-10-01), Dieffenderfer et al.
patent: 5832291 (1998-11-01), Rosen et al.
patent: 5838915 (1998-11-01), Klausmeier et al.
patent: 5860086 (1999-01-01), Crump et al.
patent: 5872963 (1999-02-01), Bitar et al.
patent: 5960211 (1999-09-01), Schwartz et al.
patent: 6002882 (1999-12-01), Garde
patent: 6021453 (2000-02-01), Klingman
patent: 6035422 (2000-03-01), Hohl et al.
patent: 6101599 (2000-08-01), Wright et al.
patent: 6119215 (2000-09-01), Key et al.
patent: 6173386 (2001-01-01), Key et al.
patent: 6195739 (2001-02-01), Wright et al.
patent: 6272621 (2001-08-01), Key et al.
patent: 6385747 (2002-05-01), Scott et al.
patent: 6442669 (2002-08-01), Wright et al.
patent: 6836838 (2004-12-01), Wright et al.
IEEE 1149.1 Device Architecture, http://www.asset-intertech.com/tutorial/arch.htm., pp. 1-4, 1998.
Digital Systems Testing and Testable Design, Miron Abramovici, et al., Computer Science Press, pp. 342-409, Copyright 1990.
The Principle Boundary-Scan Architecture, http://www.asset-intertech.com/tutorial/principle.htm, pp. 1-4, 1998.
IEEE 1149.1 Device Architecture (continued), The Test Access Port (TAP), http://www.asset-intertech.com/homepage/bscantutr/arch3.htm#TAP, pp. 1-3, 1998.
IEEE 1149.1 Device Architecture (continued), Using the Instruction Register (IR), http://www.asset-intertech.com/tutorial/arch2.htm, pp. 1-4, 1998.
Ishii et al. Cellular Array Processor CAP and Application pp. 535-544 IEEE 1988.

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