Array synchronization with counters

Details Array synchronization with counters Array synchronization with counters

2003-12-12

2009-10-13

Chan, Eddie P (Department: 2183)

Electrical computers and digital processing systems: processing

Processing architecture

Array processor

Reexamination Certificate

active

07603541

ABSTRACT:
A method is disclosed for achieving synchronization in an array of semi-synchronous devices. A processor array has an array of processor elements, wherein each of said processor elements comprises a cycle counter, and a master processor element is able to transmit control command signals to each of the other processor elements. Each processor element is such that, on receipt of a control command signal, it acts on that signal only when its cycle counter reaches a predetermined value, and the master processor element is such that it transmits control command signals only when its cycle counter takes a value which is within a predetermined range, or “safe window”. By appropriate setting of the “safe window”, it can be guaranteed that, when the master processor element transmits a control command signal to each of the other processor elements, those command control signals are acted upon at corresponding times within the other processor elements.

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