Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...
Reexamination Certificate
2000-08-21
2001-10-30
Kim, Kenneth S. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Microprocessor or multichip or multimodule processor having...
C712S011000, C712S024000, C713S400000
Reexamination Certificate
active
06311262
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to large-scale integrated circuits which, contain a plurality of individual modules with a wide variety of functions and complexity. The modules can be flexibly configured or programmed depending on the use of the system. On the one hand, the individual modules can be supplied with programs using the lowest possible instruction bandwidth, and, on the other hand, can be coordinated and synchronized. A synchronous response of the individual modules can be achieved very easily, by way of example, by permanently assigning individual bits in very long instruction words VLIW to the respective individual modules.
If such a large-scale integrated system is used, by way of example, for processing a two-dimensional image whose pixels are read in sections from an image memory, are processed pixel-by-pixel in an arithmetic and logic unit and are finally written back to the image memory, then address generators for reading from and writing to the image memory are required in addition to the arithmetic and logic unit. The address generators have to take account of the two-dimensional nature of the object to be processed during address calculation, for example using two interleaved program loops. The arithmetic and logic unit, on the other hand, need know only the total number of pixels to be processed, but not their arrangement in the memory. A single program loop is therefore sufficient for the arithmetic and logic unit. If the instructions for the address generators and for the arithmetic and logic unit are combined into an instruction word VLIW of corresponding length, however, then the resulting program unnecessarily also has two interleaved loops for portion of the program that belongs to the arithmetic and logic unit.
In the operation of such systems, the situation frequently arises that not all the modules are active at the same time. This means that transmission bandwidth to the instruction memory, which is generally located outside the integrated circuit, is wasted, since a relatively large amount of so-called NOP instructions (no operation) are also transmitted for the modules not currently needed. One possibility of saving bandwidth to the instruction memory involves the instruction words being stored in the instruction memory in compressed form, that is to say NOP instructions largely removed, and the missing NOP instructions being added again only on the path to the individual modules.
U.S. Pat. No. 5,774,737 (see European patent application EP 0 768 602 A 2) discloses an apparatus for the hierarchical and distributed control of programmable modules. There, a multiplicity of control modules interchange control information with a superordinate control unit and use control lines to drive processing modules permanently assigned to the respective control modules.
The publication by Bernhard K. Gunther: Multithreading with Distributed Functional Units, in IEEE Transactions on Computers, Vol. 46, No. 4, April 1997, pages 399-411 discloses a synchronization unit for an apparatus having a multiplicity of control and processing modules.
SUMMARY OF THE INVENTION
The object of the invention is to provide an apparatus for the hierarchical and distributed control of programmable modules in large-scale integrated systems which overcomes the above-noted deficiencies and disadvantages of the prior art devices and methods of this kind, and which achieves the lowest possible transmission bandwidth for the instruction stream between an external instruction memory and the large-scale integrated system and achieves the lowest possible power loss in the large-scale integrated system.
With the above and other objects in view there is provided, in accordance with the invention, an apparatus for hierarchical and distributed control of programmable modules in large-scale integrated systems, comprising a multiplicity of control modules interchanging control information with a superordinate control unit and communicating through control lines to drive processing modules permanently assigned to respective the control modules, a synchronization unit connected to all the control modules via synchronization lines, a dedicated instruction cache memory allocated to each the control module and whereby respective control modules are selectively connectible and disconnectible by the superordinate control unit, and/or the processing modules are selectively connectible and disconnectible by appropriate control signals on the control lines.
The invention has the particular advantage that the individual modules can be programmed in modular fashion, which is of fundamental significance as regards development and error immunity, particularly in large-scale integrated systems having many individual modules.
In accordance with an added feature of the invention, control modules are connected to the control lines via FIFO memories and the synchronization unit.
In accordance with an additional feature of the invention, the control modules are connected to further control modules via FIFO memories and the synchronization unit, and outputs of the further control modules are connected to the control lines.
In, accordance with another feature of the invention, subordinate control modules are connected to receive control information and to interchange information with the synchronization unit, the subordinate control modules supplying the control information via control lines to processing modules assigned to the subordinate control modules.
In accordance with a concomitant feature of the invention, the control modules are essentially implemented by microprograms, and the synchronization unit, and if appropriate the subordinate control modules, are substantially hardwired.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an apparatus for the hierarchical and distributed control of programmable modules in large-scale integrated systems, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
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“An Alternative Approach Towards The Design Of Control Units”, Rajiv Jain et al., 322 Microelectronics and Reliability 24, 1984, No. 6, Exeter, Great Britain, pp. 1009-1012.
“Multithreading with Distributed Functional Units”, Bernard K, Gunter, IEEE Transactions on Computers, vol. 46, No. 4, Apr., 1997, pp. 399-411.
“A Variable Instruction Stream Extension to the VLIW Architecture”, Andrew Wolfe et al., 8345 Computer Architecture News 19, Apr. 1991, No. 2, New York, pp. 2-14.
“Asynchronous Polycyclic Architecture”, Geraldo Line de Campos 12118 Second Joint International Conf. on Vector and Parallel Processing, Sep. 1992, Lyon, France, Berlin, Germany, pp. 387-398.
Hachmann Ulrich
Raab Wolfgang
Ramacher Ulrich
Greenberg Laurence A.
Infineon - Technologies AG
Kim Kenneth S.
Lerner Herbert L.
Stemer Werner H.
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