Circuit for time-sharing of configurable I/O pins

Circuits, system, and methods for processing multiple data strea

Clustered architecture in a VLIW processor

Coarse-grained look-up table architecture

Code segment default operation determination

Collation of interrupt control devices

Combined associative processor and random access memory...

Combined Instruction and address caching system using...

Combining hardware and software to provide an improved microproc

Combining results of selectively executed remaining...

Communication link control among inter-coupled multiple...

Communication link control among inter-coupled multiple...

Communication paths for enabling inter-sequencer...

Communication system for controlling intercommunication...

Communication system signal processing apparatus with ROM stored

Communications in a processor array

Communications processor for voice band telecommunications

Communications protocol processing by real time processor...

Communications system with a configurable data transfer architec

Comparators in IC with programmably controlled positive /...