Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...
Reexamination Certificate
1990-07-06
2001-05-08
Eng, David Y. (Department: 2155)
Electrical computers and digital processing systems: processing
Processing architecture
Microprocessor or multichip or multimodule processor having...
36
Reexamination Certificate
active
06230255
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to processors for voice band telecommunications and more particularly to digital processors which have the capability of processing code excited linear predictive algorithms.
2. Discussion of Related Art
Recently, cellular telephone systems have become more practical and popular. Their popularity has increased to the point where service availability will soon be unable to meet demand. It has therefore been proposed to implement a digital cellular network which incorporates predictive speech signal coding for reducing the bandwidth of transmitted speech thereby enhancing system performance and enabling time division multiplexing which significantly increases user availability.
The Telecommunication Industries Association has adopted a standard, Digital Cellular Standard IS-54, which implements a vector sum excited linear predictive (VSELP) vocoder algorithm for use in the United States. This algorithm is computationally intensive, requiring on the order of 6.45×10
6
arithmetic operations per second and 15.6 million instructions per second (MIPS).
Other areas of the world are also moving toward digital cellular systems. Japan has recently adopted a VSELP algorithm similar to the United States, and Europe is moving toward a CELP algorithm referred to as Group Special Mobile (GSM).
Currently, digital signal processors (DSPs) such as the DSP65000 family manufactured by Motorola, Inc. are available for implementing digital algorithms such as digital filters, fast fourier transforms, correlation functions, etc. Such processors have special features such as modulo addressing, hardware DO loops, 24-bit by 24-bit hardware multipliers, etc. to facilitate the large number of high precision arithmetic operations required in digital signal processing. DSPs are ideally suited for executing the VSELP and similar algorithms except that current models have too low a clock rate. The DSP65000 family, for example has a nominal clock rate of 20.48 MHz giving an execution rate of 10.24 MIPS. This can be increased to 27 MHz for an execution rate of 13.5 MIPS. To accomodate the 15.6 MIPS needed for IS-54, the clock rate would have to be increase to about 32 MHz. Such an increase would require redesign of the DSP.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a communications processor for implementing IS-54 and other computationally intensive digital signal processing algorithms using conventionally available components operating at conventional clock rates.
Another object of the present invention is to provide a communications processor which contains a user programmable functionality permitting the execution of instructions in addition to the computationally intensive digital signal processing algorithm without adversely affecting execution of the algorithm.
A further object of the present invention is to provide a communications processor implemented on a single integrated circuit chip.
In accordance with the above and other objects, the communications processor of the present invention comprises, in a single integrated circuit chip, the combination of a central processing unit (CPU) having an execution unit with an arithmetic logic unit and accumulators, a program counter, memory, a clock generator, a timer, a bus interface, chip select outputs, and an interrupt processor; a digital signal processor (DSP) having an instruction set to carry out a digital signal processing algorithm, an execution unit for carrying out multiply and accumulate operations and an external interface; an address bus connected between the CPU and the DSP; a data bus connected between the CPU and the DSP; and a static scheduler for statically scheduling execution of the signal processing algorithm between the digital signal processor and the CPU.
In accordance with other aspects, the digital signal processing algorithm may be a digital speech processing algorthim and the scheduler may be contained in the DSP and may include an interrupt generator for generating interrupts to the CPU to command execution by the CPU of portions of the speech processing algorithm. The CPU interrupt processor processes the interrupts from the DSP as nonmaskable interrupt signals to ensure that execution of the algorithm takes priority over other programs.
To exploit the advantages of the DSP and CPU, the static scheduler partitions execution of the signal processing algorithm to cause all multiply and multiply-accumulate operations to be executed in the DSP and all other operations such as add, subtract, divide, compare, etc. to be executed in the CPU.
In accordance with other aspects of the invention, the speech processing algorithm may be a code excited linear predictive coding algorithm and, in particular, may be a vector sum excited linear predictive coding algorithm.
The CPU includes operating system support for permitting user programming of the CPU. The static scheduler controls the operating system support to give priority to execution of the signal processing algorithm.
The static scheduler effects simultaneous operation of the CPU and DSP during portions of the execution of said signal processing algorithm.
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Asghar Safdar M.
Bartkowiak John G.
Advanced Micro Devices , Inc.
Eng David Y.
Foley & Lardner
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