Accessing byte lines from dual memory blocks and aligning...
Aligning instructions using a variable width alignment...
Apparatus and method for aligning variable-width...
Apparatus and method for parallel decoding of variable-length in
Control transfer indication in predecode which identifies contro
Data processing apparatus and method for moving data between...
Determination of execution resource allocation based on...
Digital signal processor having data alignment buffer for perfor
Digital signal processor with bit FIFO
Dual in-line buffers for an instruction fetch unit
Efficient method for fetching instructions having a...
Embedding two different instruction sets within a single long in
Execution unit chaining for single cycle extract instruction hav
Forwarding instruction byte blocks to parallel scanning...
Functional bit identifying a prefix byte via a particular state
High performance superscalar alignment unit
Instruction alignment unit employing dual instruction queues for
Instruction alignment unit for routing variable byte-length...
Instruction cache alignment mechanism for branch targets...
Instruction fetch unit aligner for a non-power of two size...