Embedding two different instruction sets within a single long in

Details Embedding two different instruction sets within a single long in Embedding two different instruction sets within a single long in

1998-01-05

2000-06-27

Kim, Kenneth S.

Electrical computers and digital processing systems: processing

Instruction alignment

712 24, 712213, 712215, G06F 938

Patent

active

060818840

ABSTRACT:
A microprocessor optimized to execute two instruction sets in a long instruction word (LIW) format. One instruction set may have variable length instructions. The microprocessor has an alignment unit configured to detect variable length instructions as they are fetched from an instruction cache, and then embed the variable length instructions within a long instruction word. The long instruction words are stored in a central window until they are executed by a number of functional units. A number of the microprocessor's functional units may be configured to execute instructions from both instruction sets. These dual instruction set-capable functional units may be used in conjunction with an MROM unit configured to translate a subset of instructions from one instruction set into less complex instructions in either instruction set. The central window may be configured to shift the order of the long instruction words before they are issued in order to minimize the amount of time the functional units are idle. The central window may be replaced altogether by a series of reservation stations. A method for operating a microprocessor with two instruction sets is also disclosed.

REFERENCES:
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patent: 5442762 (1995-08-01), Kato et al.
patent: 5774737 (1998-06-01), Nakano
patent: 5852741 (1998-12-01), Jacobs et al.
patent: 5922065 (1999-07-01), Hull et al.
patent: 5930508 (1999-07-01), Faraboschi et al.
Halfhill, "Beyond Pentium II", BYTE Magazine, Dec. 1997, 9 pages.

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