Apparatus and method for parallel decoding of variable-length in

Details Apparatus and method for parallel decoding of variable-length in Apparatus and method for parallel decoding of variable-length in

1997-02-27

1999-08-24

Treat, William M.

Electrical computers and digital processing systems: processing

Instruction alignment

712 23, 712206, 712207, 712210, 712212, 712213, 712215, G06F 930

Patent

active

059419806

ABSTRACT:
A process is provided for determining the beginning and ending of each instruction of a variable length instruction. Data lines are stored in a first memory area which illustratively is an instruction cache. Each data line comprises a sequence of data words that are stored at sequential address in a main memory. The data lines contain multiple encoded variable length instructions that are contiguously stored in the main memory. Multiple indicators are stored in a second memory area, including one indicator associated with each data word of the data lines stored in the first memory area. Each indicator indicates whether or not its associated data word is the initial data word of a variable length instruction. A sequence of data words may be fetched from the cache. The fetched sequence of data words includes a starting data word and at least the number of data words in the longest permissible instruction. Plural indicators (i.e., a vector of indicators) are also fetched from the second memory area including one indicator associated with each of the data words of the fetched sequence. Using the indicators as delimiters of the sequence of to-be-decoded instructions, one or more non-overlapping subsequences of the sequence of data words are identified, wherein each subsequence of data words is comprised in a different, sequential to-be-decoded instruction. Each subsequence of data words is then decoded as a separate instruction.

REFERENCES:
patent: 4539635 (1985-09-01), Boddie et al.
patent: 4598358 (1986-07-01), Boddie et al.
patent: 5202967 (1993-04-01), Matsuzaki et al.
patent: 5337415 (1994-08-01), DeLano et al.
patent: 5448746 (1995-09-01), Eickemeyer et al.
patent: 5450605 (1995-09-01), Grochowski et al.
patent: 5459844 (1995-10-01), Eickemeyer et al.
patent: 5488710 (1996-01-01), Sato et al.
patent: 5600806 (1997-02-01), Brown et al.
patent: 5724422 (1998-03-01), Shang et al.
patent: 5758116 (1998-05-01), Lee et al.
D. Anderson, Pentium Processor System Architecture, 2nd ed. (1995); Intel, A Tour of the Pentium.RTM. Pro Processor Microarchitecture (http://intel.com/procs/ppro/info/p6 white/index.htm).

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