Dual in-line buffers for an instruction fetch unit

Details Dual in-line buffers for an instruction fetch unit Dual in-line buffers for an instruction fetch unit

1998-12-03

2001-11-20

Treat, William M. (Department: 2783)

Electrical computers and digital processing systems: processing

Instruction alignment

C712S024000, C712S206000

Reexamination Certificate

active

06321325

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to microprocessors, and more particularly, to dual in-line buffers for an instruction fetch unit.
BACKGROUND
A microprocessor typically includes a cache memory for storing copies of the most recently used memory locations. The cache memory generally is smaller and faster than main memory (e.g., disk). A microprocessor also typically includes an instruction prefetch unit that is responsible for prefetching instructions for a CPU (Central Processing Unit). In particular, an instruction cache unit is typically organized in a way that reduces the amount of time spent transferring instructions having a power of two size into the prefetch unit. For example, a 256-bit bus (256 bits=4×8 bytes=32 bytes) connecting the instruction cache unit and the prefetch unit allows a 32-byte instruction prefetch unit to fetch 32 bytes of instruction data in a single cycle of the microprocessor.
SUMMARY
The present invention provides dual in-line buffers for an instruction fetch unit. For example, the present invention provides a cost-effective and high performance apparatus for an instruction fetch unit (IFU) of a microprocessor that executes instructions having a non-power of two size.
In one embodiment, an apparatus for an instruction fetch unit includes a first line buffer of dual in-line buffers for storing a first instruction cache line having a power of two size, and a second line buffer of the dual in-line buffers for storing a second instruction cache line having a power of two size. An instruction having a non-power of two size can span both the first line buffer and the second line buffer.
In one embodiment, an apparatus for a microprocessor includes an instruction cache unit that includes power of two size-aligned instruction cache lines (e.g., 32-byte instruction cache lines), and an instruction fetch unit connected to the instruction cache unit. The instruction fetch unit includes dual in-line buffers that store a first instruction cache line and a second instruction cache line, in which the first instruction cache line and the second instruction cache line include a non-power of two size instruction (e.g., 5, 10, 15, or 20 bytes of instruction data). For example, the dual in-line buffers can be implemented as two registers of the instruction fetch unit.
Other aspects and advantages of the present invention will become apparent from the following detailed description and accompanying drawings.


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