Electrical computers and digital processing systems: processing – Instruction alignment
Patent
1998-04-23
2000-10-17
Follansbee, John A.
Electrical computers and digital processing systems: processing
Instruction alignment
712206, 712207, 712213, 712217, G06F 9312
Patent
active
061346497
ABSTRACT:
A processor is configured to predecode instruction bytes prior to storing them in an instruction cache. The predecode information generated by the processor includes instruction boundary indications identifying which of the instruction bytes are boundaries of instructions and control transfer indications identifying which of the instructions are control transfer instructions. The combination of the control transfer indications and the instruction boundary indications allows the branch prediction mechanism to locate the branch instructions in a group of instruction bytes fetched from instruction cache by scanning the control transfer and instruction boundary indications. In one embodiment, the branch prediction mechanism attempts to predict up to two branch instructions per clock cycle. Accordingly, the branch prediction mechanism scans the control transfer and instruction boundary indications to locate the first two branch instructions within a group of instruction bytes fetched from the instruction cache. In one embodiment, the instruction boundary indications comprise a start bit corresponding to each instruction byte. The start bit is set if the corresponding instruction byte is the initial byte of an instruction, and clear if the corresponding instruction byte is not the initial byte of instruction. The control transfer indications may similarly comprise a control transfer bit corresponding to each instruction byte. If a byte is indicated to be the initial byte of an instruction via the start bit, the control transfer bit is used to indicate whether or not the instruction is a control transfer instruction.
REFERENCES:
patent: 4502111 (1985-02-01), Riffe et al.
patent: 5101341 (1992-03-01), Circello et al.
patent: 5129067 (1992-07-01), Johnson
patent: 5155820 (1992-10-01), Gibson
patent: 5233696 (1993-08-01), Suzuki
patent: 5313605 (1994-05-01), Huck et al.
patent: 5337415 (1994-08-01), DeLano et al.
patent: 5438668 (1995-08-01), Coon et al.
patent: 5459844 (1995-10-01), Eickemeyer et al.
patent: 5488710 (1996-01-01), Sato et al.
patent: 5499204 (1996-03-01), Barrera et al.
patent: 5513330 (1996-04-01), Stiles
patent: 5557271 (1996-09-01), Rim et al.
patent: 5559975 (1996-09-01), Christie et al.
patent: 5560028 (1996-09-01), Sachs et al.
patent: 5566298 (1996-10-01), Boggs et al.
patent: 5586276 (1996-12-01), Growchowski et al.
patent: 5586277 (1996-12-01), Brown
patent: 5598544 (1997-01-01), Oshima
patent: 5600806 (1997-02-01), Brown et al.
patent: 5625787 (1997-04-01), Mahin et al.
patent: 5630082 (1997-05-01), Yao et al.
patent: 5644744 (1997-07-01), Mahin et al.
patent: 5689672 (1997-11-01), Witt et al.
patent: 5692168 (1997-11-01), McMahan
patent: 5729707 (1998-03-01), Maki
patent: 5758114 (1998-05-01), Johnson et al.
patent: 5758116 (1998-05-01), Lee et al.
patent: 5872943 (1999-02-01), Pickett et al.
patent: 5935238 (1999-08-01), Talcott et al.
patent: 5968163 (1999-10-01), Narayn et al.
patent: 5987235 (1999-11-01), Tran
Tamasulo, "An Efficient Algorithm For Exploiting Multiple Arithmetic Units," 1967, IBM Journal, pp. 25-33.
Minagawa, "Predecoding Mechanism for Superscalar Architecture," 1991, IEEE Publication, pp. 21-24.
XP000212073 Ditzel, et al., "Branch Folding in the CRISP Microprocessor: Reducing Branch Delay to Zero," AT&T BELL Laboratories, 14.sup.th Annual International Symposium on Computer Architecture, Jun. 2-5, 1987, pp. 2-9.
XP000364329 Gonzalez, et al., "Reducing Branch Delay to Zero in Pipelined Processors," IEEE Transactions on Computers, vol. 42, No. 3, Mar. 1993, pp. 363-371.
International Search Report for International Application No. PCT/US98/22050 mailed Feb. 10, 1999.
Advanced Micro Devices , Inc.
Follansbee John A.
Merkel Lawrence J.
Patel Gautam R.
LandOfFree
Control transfer indication in predecode which identifies contro does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Control transfer indication in predecode which identifies contro, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Control transfer indication in predecode which identifies contro will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-479531