Electrical computers and digital processing systems: processing – Instruction alignment
Reexamination Certificate
1998-12-03
2001-11-06
Treat, William M. (Department: 2783)
Electrical computers and digital processing systems: processing
Instruction alignment
C712S024000, C712S206000
Reexamination Certificate
active
06314509
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to microprocessors, and more particularly, to an efficient method for fetching instructions having a non-power of two size.
BACKGROUND
A microprocessor typically includes a cache memory for storing copies of the most recently used memory locations. The cache memory generally is smaller and faster than main memory (e.g., disk). A microprocessor also typically includes an instruction prefetch unit that is responsible for prefetching instructions for a CPU (Central Processing Unit). In particular, an instruction cache unit is typically organized in a way that reduces the amount of time spent transferring instructions having a power of two size into the prefetch unit. For example, a 256-bit bus (256 bits=4×8 bytes=32 bytes) connecting the instruction cache unit and the prefetch unit allows a 32-byte instruction prefetch unit to fetch 32 bytes of instruction data in a single cycle of the microprocessor.
SUMMARY
The present invention provides an efficient method for fetching instructions having a non-power of two size. For example, the present invention provides a cost-effective and high performance method for an instruction fetch unit of a microprocessor that executes instructions having a non-power of two size.
In one embodiment, a method for fetching instructions having a non-power of two size includes fetching a first instruction cache line having a power of two size for storage in a first line buffer of an instruction fetch unit of a microprocessor, fetching a second instruction cache line having a power of two size for storage in a second line buffer of the instruction fetch unit, and extracting and aligning instruction data stored in the first line buffer and the second line buffer to provide an instruction having a non-power of two size.
In one embodiment, a method for fetching instructions having a non-power of two size includes fetching at least two sequential cache lines of instruction data having a power of two size for storage in dual in-line buffers of an instruction fetch unit, and extracting and aligning a non-power of two size instruction that is stored in the dual in-line buffers. Specifically, two sequential instruction cache lines each having a power of two size (e.g., 32 bytes) are stored in the dual in-line buffers. An instruction having a non-power of two size (e.g., 5 bytes, 10 bytes, 15 bytes, or 20 bytes) is extracted and aligned from the dual in-line buffers in a single clock cycle of the microprocessor. More specifically, an instruction cache line is stored in an instruction cache unit, in which the stored instruction cache line is power of two size-aligned. The instruction cache line is fetched and stored in a first line of the dual in-line buffers. Power of two size instruction cache data (e.g., 32 bytes of instruction cache data) is extracted from the dual in-line buffers and then transmitted to an instruction aligner. A rotate and truncate (RAT) unit of the instruction aligner rotates and truncates the power of two size instruction data to provide an instruction having a non-power of two size, which is then transmitted to an instruction queue for buffering before execution. For example, this method can be used for a microprocessor that implements an instruction set architecture, which includes instructions having a non-power of two size.
Other aspects and advantages of the present invention will become apparent from the following detailed description and accompanying drawings.
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Murphy Graham R.
Tremblay Marc
Skjerven Morrill & MacPherson LLP
Sun Microsystems Inc.
Terrile Stephen A.
Treat William M.
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