Simple load and store disambiguation and scheduling at...

Simultaneously assigning corresponding entry in multiple...

SMT flush arbitration

Software controllable register map

Special instruction register including allocation field utilized

Speculation pointers to identify data-speculative operations...

Speculative counting of performance events with rewind counter

Speculative execution control with programmable indicator...

Speculative execution of a load instruction by associating...

Speculative generation at address generation stage of...

Speculative instructions exection in VLIW processors

Speculative issue of instructions under a load miss shadow

Speculative renaming of data-processor registers

Split data-flow scheduling mechanism

Stall control

Stall-free pipelined cache for statically scheduled and...

Stick and spoke replay with selectable delays

Stitching parcels

Stopping replay tornadoes

Store load forward predictor training