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Scan chains for out-of-order load/store execution control

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
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Scheduling instructions in a cascaded delayed execution...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Reducing an impact of a stall or pipeline bubble
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Scheduling instructions with different latencies

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
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Scheduling operations using a dependency matrix

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
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Scoreboard mechanism for serialized string operations...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Scoreboarding – reservation station – or aliasing
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Secondary reorder buffer microprocessor

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Commitment control or register bypass
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Segmented pipeline flushing for mispredicted branches

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
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Selected register decode values for pipeline stage register...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Commitment control or register bypass
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Selecting multiple threads for substantially concurrent...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
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Selecting register or previous instruction result bypass as sour

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Commitment control or register bypass
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Selective canonizing on mode transitions

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Scoreboarding – reservation station – or aliasing
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Selective execution of deferred instructions in a processor...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Reducing an impact of a stall or pipeline bubble
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Selective flush of shared and other pipeline stages in a...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
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Selective suppression of register renaming

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Scoreboarding – reservation station – or aliasing
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Selective vertical and horizontal dependency resolution via...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
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Selectively deferring instructions issued in program order...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Reducing an impact of a stall or pipeline bubble
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Selectively powered retirement unit using a partitioned...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Commitment control or register bypass
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Shared dependency checking for status flags

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Scoreboarding – reservation station – or aliasing
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Shared resource queue for simultaneous multithreading...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Scoreboarding – reservation station – or aliasing
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Simple load and store disambiguation and scheduling at...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
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