Scan chains for out-of-order load/store execution control
Scheduling instructions in a cascaded delayed execution...
Scheduling instructions with different latencies
Scheduling operations using a dependency matrix
Scoreboard mechanism for serialized string operations...
Secondary reorder buffer microprocessor
Segmented pipeline flushing for mispredicted branches
Selected register decode values for pipeline stage register...
Selecting multiple threads for substantially concurrent...
Selecting register or previous instruction result bypass as sour
Selective canonizing on mode transitions
Selective execution of deferred instructions in a processor...
Selective flush of shared and other pipeline stages in a...
Selective suppression of register renaming
Selective vertical and horizontal dependency resolution via...
Selectively deferring instructions issued in program order...
Selectively powered retirement unit using a partitioned...
Shared dependency checking for status flags
Shared resource queue for simultaneous multithreading...
Simple load and store disambiguation and scheduling at...