Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Reducing an impact of a stall or pipeline bubble
Reexamination Certificate
2006-09-26
2006-09-26
Ellis, Richard L. (Department: 2183)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
Reducing an impact of a stall or pipeline bubble
C712S216000, C712S215000
Reexamination Certificate
active
07114060
ABSTRACT:
One embodiment of the present invention provides a system that facilitates deferring execution of instructions with unresolved data dependencies as they are issued for execution in program order. During a normal execution mode, the system issues instructions for execution in program order. Upon encountering an unresolved data dependency during execution of an instruction, the system generates a checkpoint that can subsequently be used to return execution of the program to the point of the instruction. Next, the system executes subsequent instructions in an execute-ahead mode, wherein instructions that cannot be executed because of an unresolved data dependency are deferred, and wherein other non-deferred instructions are executed in program order.
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Publication entitled “Beating in-order Stalls with “Flea-Flicker” two-pass Pipelining”, by Ronald D. Barnes et al., Proceedings of the 36thInternational Symposium on Microarchitecture, IEEE, 2003.
Chaudhry Shailender
Tremblay Marc
Ellis Richard L.
Park Vaughan & Fleming LLP
Sun Microsystems Inc.
Zalepa George D.
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