Delayed deallocation of an arithmetic flags register

Dependence-chain processing using trace descriptors having...

Dependence-chain processing using trace descriptors having...

Dependency checking for reconfigurable logic

Dependency table for reducing dependency checking hardware

Dependency table for reducing dependency checking hardware

Design structure for single hot forward interconnect scheme...

Detecting raw hazards in an object-addressed memory...

Detection of data hazards between instructions by decoding...

Determining register availability for register renaming

Determining successful completion of an instruction by...

Device and method for processing instructions based on...

Different register data indicators for each of a plurality...

Digital signal processor computation core with pipeline...

Digital signal processor having distributed register file

Dual-target block register allocation

Dynamic concurrent atomic execution

Dynamic data dependence tracking and its application to...

Dynamic instruction dependency monitor and control system

Dynamic instruction dependency monitor and control system