Bus protocol for locked cycle cache hit
Bus snooping for cache coherency for a bus without built-in...
Bus timing protocol for a data storage system
Bypass custom array and related method for implementing ROM...
Bypassing a nonpaged pool controller when accessing a remainder
Byte alignment circuitry
Byte alignment circuitry
Byte swap operation for a 64 bit operand
Byte-wise tracking on write allocate
Byte-wise write allocate with retry tracking
Byte-writable two-dimensional FIFO buffer having storage locatio
Cacche memory employing dynamically controlled data array start
Cachability attributes of virtual addresses for optimizing perfo
Cache access control system
Cache accumulator memory for performing operations on block...
Cache address conflict mechanism without store buffers
Cache addressing mechanism that adapts multi-dimensional address
Cache affinity scheduling method for multi-processor nodes in a
Cache allocation mechanism for biasing subsequent...
Cache allocation mechanism for modified-unsolicited cache...