Byte-writable two-dimensional FIFO buffer having storage locatio

Details Byte-writable two-dimensional FIFO buffer having storage locatio Byte-writable two-dimensional FIFO buffer having storage locatio

1996-10-18

1999-10-26

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Memory configuring

395872, 711154, G06F 1200

Patent

active

059745169

ABSTRACT:
A FIFO storage circuit stores data transferred over a data bus in data groups having of one or more data units. The FIFO buffer includes a number of storage locations each configured to store a single unit of data. Each data groups on the data bus is accompanied by data-size information. A storage-location availability decoder receives the data-size information and allocates a number of consecutive storage locations in the FIFO storage circuit to allow for storage of the incoming data group. The FIFO then stores each unit of the data group, along with a data tag common to each unit, in consecutive storage locations. The next stored data group is then assigned a new data tag. The FIFO storage circuit reads from the storage locations in order of data tag. Checking consecutive storage locations for equivalent data tags enables the FIFO storage circuit to output the appropriate number of units for each data group. Further, assigning unique sequential data tags to each data group allows the FIFO storage circuit to read the contents of FIFO buffer 200 in the appropriate order.

REFERENCES:
patent: 5003469 (1991-03-01), Kamiyama et al.
patent: 5465079 (1995-11-01), Bouchard et al.
patent: 5535369 (1996-07-01), Wells et al.
patent: 5563920 (1996-10-01), Fimoff et al.

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