Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-09-05
2006-09-05
Bragdon, Reginald G. (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S134000, C711S136000
Reexamination Certificate
active
07103721
ABSTRACT:
An improved method and apparatus for selecting invalid members as victims in a least recently used cache system. An invalid cache line selection unit has an input connected to a cache directory and an output connected to a most recently used update logic. In response to a miss in the cache, an invalid cache line is identified from information in the cache directory by the invalid cache line selection unit. This invalid cache line is updated to be the next victim by the most recently used update logic, rather than attempting to override the current victim selection by a least recently used victim selection logic. The next victim also may be selected in response to a cache hit in which information from the cache directory also is read.
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Cargnoni Robert Alan
Guthrie Guy Lynn
Starke William John
Stuecheli Jeffrey Adam
Adams-Moe Mary
Bragdon Reginald G.
International Business Machines - Corporation
Ko Daniel
Tyson Thomas E.
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