Cache addressing mechanism that adapts multi-dimensional address

Details Cache addressing mechanism that adapts multi-dimensional address Cache addressing mechanism that adapts multi-dimensional address

1996-08-02

1998-07-07

Lane, Jack A.

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

Addressing cache memories

G06F 1200

Patent

active

057784086

ABSTRACT:
A cache addressing mechanism particularly useful for a data cache used with a floating point processor for spreadsheet calculations where the spreadsheet program has column and row address fields in a single address. The most active bits in the column and row address fields are hashed to provide set selection bits. The most significant bit of the most active bits of one field is exclusively ORed with the least significant bit of the most active bits of the other field as part of the hashing.

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patent: 5392410 (1995-02-01), Liu
Liu, "XOR Randomization in Cache Congruence Class Indexing" IBM Technical Disclosure Bulletin, vol. 27, No. 2 Jul. 1984, p. 1097.

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