Cachability attributes of virtual addresses for optimizing perfo

Details Cachability attributes of virtual addresses for optimizing perfo Cachability attributes of virtual addresses for optimizing perfo

1995-02-27

1999-12-21

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Address formation

Address mapping

711202, 711206, 711207, 711122, 711145, 711146, 711156, 711 3, G06F 1200

Patent

active

060063122

ABSTRACT:
A separate cacheable-in-virtual-cache attribute bit (CV) is maintained for each page of memory in the translation table maintained by the operating system. The CV bit indicates whether the memory addresses on the page to which the translation table entry refers are cacheable in virtually indexed caches. According to a first embodiment, when there are two or more aliases which are not offset by multiples of the virtual cache size, all of the aliases are made non-cacheable in virtually indexed caches by deasserting the CV bits for all aliases. With regards to the contents of the translation lookaside buffer (TLB), the translations for all aliases may simultaneously coexist in the TLB because no software intervention is required to insure data coherency between the aliases. According to second and third embodiments of the present invention, when there are two or more aliases which are not offset by multiples of the virtual cache size, only one of those aliases may remain cacheable in virtual caches. For the other aliases, the CV bits for the translation pages containing those aliases are deasserted. The operating system has the responsibility of flushing data from the virtually indexed internal cache before deasserting the CV attribute for a page. The second embodiment allows the newer mapping to a physical address to remain in the first-level cache, while the third embodiment allows the older alias to remain in the first-level cache when a newer alias is mapped.

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