Instruction decoding mechanism for reducing execution time by ea
Instruction fetch on demand for uncacheable memory which avoids
Instruction pair detection and pseudo ports for cache array
Instruction pair detection and pseudo ports for cache array
Instruction pre-fetching of a cache line within a processor
Instruction prefetch caching for remote memory
Instruction processing unit capable of efficiently accessing the
Instruction processor write buffer emulation using embedded...
Instruction set for a content addressable memory array with read
Instruction set for efficient bit stream and byte stream I/O
Instruction set for efficient bit stream and byte stream I/O
Instruction unit having a partitioned cache
Instruction-assisted cache management for efficient use of...
Instructions for test & set with selectively enabled...
Instrumentation device for a machine with non-uniform memory...
Integral modular cache for a processor
Integrated bus bridge and memory controller that enables data st
Integrated cache and directory structure for multi-level caches
Integrated cache buffers
Integrated cache memory with system control logic and adaptation