Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – Addressing cache memories
Reexamination Certificate
2000-02-14
2002-06-25
Bragdon, Reginald G. (Department: 2186)
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
Addressing cache memories
C711S128000, C711S172000, C711S212000, C365S051000
Reexamination Certificate
active
06412038
ABSTRACT:
BACKGROUND
1. Field of the Disclosure
The present disclosure pertains to the field of cache memories and particularly to the field of cache memories integrated with a data processing component.
2. Description of Related Art
Providing a number of cache size options for a product such as a microprocessor having an integrated cache may be highly beneficial. Different cache sizes typically have relatively predictable impacts on performance. Therefore, offering products with different cache sizes advantageously allows one to market the different products at different performance levels.
Moreover, the different cache sizes typically translate substantially directly into total area required for the integrated circuit die. Accordingly, the price of the die may be partially controlled by choosing the amount of cache memory to include. Unfortunately, typical caches on integrated circuits with other processing logic are not easily resized such that the entire die size can be changed.
In some prior art systems, system caches remain apart from integrated circuits such as microprocessors. For example, some of the original Pentium™ Processors available from Intel® Corporation of Santa Clara, Calif. did not include a second level (L2) cache. A separate system cache may have been used, and that cache size could be adjusted by altering the particular cache component plugged into the system and perhaps the control logic used in the system. Later, some Pentium Processors included an L2 cache in a multi-chip module. In these processors, discrete static random access memory (SRAM) chips were included within the same module. Again, by altering the number or size of the SRAM chips, the size of the L2 cache was easily variable.
Currently, some processors integrate the L2 cache on die. It is expected that L2 and/or other additional such integration will continue in the future. Unfortunately, when a cache (or other memory structure) is integrated onto a single integrated circuit which includes other logic, changing the cache size typically becomes more difficult that merely replacing a module such as a discrete SRAM or a system level cache chip. The control logic for the cache (e.g., sense amps, set and way control logic, tag control logic, and the like) is not inherently divided as is a cache array and therefore may be integrated or synthesized within a region such that portions may not be easily excised. Moreover, a cache control circuit for an integrated cache typically is not designed to operate properly if a portion of the cache array is removed. A prior art cache array typically expects certain responses from the array and would not function properly if portions of the array were removed.
For example, a prior art processor
100
is shown in FIG.
1
. The processor includes a cache
110
that has cache array(s)
130
(e.g., data, parity, tag, etc.) which may be organized into various set and way arrangements. Control logic
120
is a single block that communicates with and controls the array(s)
130
. Thus, there is no simple manner of removing sets or ways.
Additionally, the overhead of altering a large integrated circuit is indeed typically quite substantial. For example, integrated circuits are typically produced using a series of optical masks. These masks are generally produced after a product design is complete, validation is performed, and a tapeout process is completed. Any alteration of the actual circuitry involved requires that substantial time consuming validation be again performed. Thus, the unified nature of the control block and/or any logic sharing that requires alteration to change cache sizes may detrimentally increase the time required to implement such a change.
Moreover, a traditional integrated cache is typically physically placed on a die in a convenient fashion with respect to the other functional blocks. This typically results in a cache being isolated to a portion of any axis of the die. For example, in
FIG. 1
, the cache occupies only a portion of both of the X and Y axes. A removal of either a set or a way would create a hole in any rectangular die. Thus, removing a portion of the cache would not help reduce costs as the die size would remain the same (assuming traditional rectangular die lines are maintained). In order to easily change the size of the cache, the logic of the entire processor
100
may need to be rearranged, again requiring time consuming validation steps to be performed. Die re-arrangement also typically alters distances between some signal drivers and receivers, thereby disadvantageously altering timing arrangements between circuits and potentially requiring accommodating modification.
Thus, size changes for traditional integrated caches may disadvantageously require time consuming circuit changes and validation due to the alteration of control circuitry. Moreover, traditional caches may not be physically situated to allow a straightforward die size alteration in conjunction with a cache size change.
REFERENCES:
patent: 5014195 (1991-05-01), Farrell et al.
patent: 5202968 (1993-04-01), Sato
patent: 5812418 (1998-09-01), Lattimore et al.
patent: 5857214 (1999-01-01), Dey
patent: 0 285 172 (1988-03-01), None
patent: 0 549 508 (1992-11-01), None
patent: WO 99/13404 (1998-08-01), None
Bragdon Reginald G.
Draeger Jeffrey S.
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