Instruction set for efficient bit stream and byte stream I/O

Details Instruction set for efficient bit stream and byte stream I/O Instruction set for efficient bit stream and byte stream I/O

2008-09-02

2008-09-02

Kim, Matt (Department: 2186)

Electrical computers and digital processing systems: memory

Address formation

Slip control, misaligning, boundary alignment

Reexamination Certificate

active

10686882

ABSTRACT:
A system and method provide unaligned load/store functionality for a processor that supports only aligned load/store instructions. An exemplary embodiment includes an extension adapter including registers for storing data and load/store buffers for realigning data. A processor executes aligned load/store instructions that transfer data in multiples of bytes. Instructions are included for transferring data between memory and the load/store buffers, initializing and transferring data, initializing and transferring data in numbers of bits, advancing or offsetting a data pointer, and for flushing the load/store buffers. In a preferred embodiment, the extension adapter comprises a wide register file for buffering full words of data, load/store buffers formed from multiple single-bit registers for buffering data bits and streaming data for use by the processor, and address generators for pointing to data or memory addresses.

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