Instruction pre-fetching of a cache line within a processor

Details Instruction pre-fetching of a cache line within a processor Instruction pre-fetching of a cache line within a processor

1995-10-06

1999-01-12

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Address formation

Generating prefetch, look-ahead, jump, or predictive address

395383, G06F 1200

Patent

active

058601503

ABSTRACT:
An apparatus for fetching data from a main memory into a primary cache memory of a processor. Instruction fetch requests are generated by the processor and assigned a priority level according to the predicted accuracy of the fetch request. The priority levels of different fetch requests are compared and the highest priority level fetch request is serviced first. An instruction cache line address N+1 is pre-fetched if there is a cache miss in the primary cache memory on address N+1.

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