Instruction decoding mechanism for reducing execution time by ea

Details Instruction decoding mechanism for reducing execution time by ea Instruction decoding mechanism for reducing execution time by ea

1997-09-30

1999-01-12

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Address formation

Combining two or more values to create address

711214, 395381, G06F 935

Patent

active

058601554

ABSTRACT:
The mechanism includes a virtual address detecting circuit for detecting the virtual address of the instruction code. When a virtual address is detected, an indicating signal is generated, which is then sent to an indirect address register to register the indirect address of the instruction code. Thereafter, an indirect address replacing circuit is used to decode and replace the indirect address registered in and sent from the indirect address register with a direct address. In the absence of the virtual address, the direct address is allowed to pass through the indirect address replacing circuit.

REFERENCES:
patent: 4354231 (1982-10-01), Carlsson et al.
patent: 4439828 (1984-03-01), Martin
patent: 4907147 (1990-03-01), Saito et al.
patent: 5239633 (1993-08-01), Terayama et al.
patent: 5247639 (1993-09-01), Yamahata

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