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Low latency buffer control system and method

Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
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Low latency coherency protocol for a multi-chip...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Low latency lock for multiprocessor computer system

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
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Low latency memory access and synchronization

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
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Low latency memory access and synchronization

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
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Low latency memory read with concurrent pipe lined snoops

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Low latency message passing mechanism

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Low latency request dispatcher

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
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Low latency request dispatcher

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
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Low latency request dispatcher

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
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Low latency synchronous memory performance switching using...

Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
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Low locality-of-reference support in a multi-level cache...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Low occupancy protocol for managing concurrent transactions with

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
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Low overhead access to shared on-chip hardware accelerator...

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
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Low overhead memory management system and method

Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
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Low overhead method for selecting and updating an entry in a...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Low overhead snapshot in a storage array using a...

Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
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Low power cache architecture

Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
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Low power cache architecture

Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
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Low power cache operation through the use of partial tag...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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