Low locality-of-reference support in a multi-level cache...

Details Low locality-of-reference support in a multi-level cache... Low locality-of-reference support in a multi-level cache...

2005-04-07

2009-08-25

Ellis, Kevin L (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S133000, C711S136000, C711S144000, C711S145000, C711S159000

Reexamination Certificate

active

07581065

ABSTRACT:
A processor includes a multi-level cache hierarchy where locality information property such as a Low Locality of Reference (LLR) property is associated with a cache line. The LLR cache line retains the locality information and may move back and forth within the cache hierarchy until evicted from the outer-most level of the cache hierarchy.

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