Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
2007-03-09
2010-10-05
Thomas, Shane M (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S163000, C710S036000, C712S034000
Reexamination Certificate
active
07809895
ABSTRACT:
In one embodiment, a method is contemplated. Access to a hardware accelerator is requested by a user-privileged thread. Access to the hardware accelerator is granted to the user-privileged thread by a higher-privileged thread responsive to the requesting. One or more commands are communicated to the hardware accelerator by the user-privileged thread without intervention by higher-privileged threads and responsive to the grant of access. The one or more commands cause the hardware accelerator to perform one or more tasks. Computer readable media comprises instructions which, when executed, implement portions of the method are also contemplated in various embodiments, as is a hardware accelerator and a processor coupled to the hardware accelerator.
REFERENCES:
patent: 4779188 (1988-10-01), Gum et al.
patent: 2002/0062459 (2002-05-01), Lasserre et al.
patent: 2003/0028751 (2003-02-01), McDonald et al.
patent: 2004/0128507 (2004-07-01), McKenney et al.
patent: 2004/0160835 (2004-08-01), Altman et al.
patent: 2004/0237062 (2004-11-01), Zeidman et al.
patent: 2005/0228936 (2005-10-01), Kuo et al.
patent: 2005/0257186 (2005-11-01), Zilbershlag
patent: 2006/0056517 (2006-03-01), MacInnis et al.
patent: 2006/0200802 (2006-09-01), Mott et al.
patent: 2006/0230213 (2006-10-01), Tousek et al.
patent: 2007/0061547 (2007-03-01), Jordan et al.
patent: 2007/0067543 (2007-03-01), Fujise et al.
patent: 2007/0143287 (2007-06-01), Adl-tabatabai et al.
patent: 2007/0157211 (2007-07-01), Wang et al.
patent: 2008/0104362 (2008-05-01), Buros et al.
U.S. Appl. No. 11/684,358, filed Mar. 9, 2007.
Mackerras, et al., “Operating System Exploitation of the POWER5 System,” IBM, Sep. 2005, vol. 49, No. 4/5, pp. 533-539.
Kongetira, et al., “Niagara: A 32-Way Multithreaded Sparc Processor,” IEEE, 2005, pp. 21-29.
Keromytis, et al., “The Design of the OpenBSD Cryotpgraphic Framework,” Proc. USENIX Technical Conference 2003, 16 pages.
Lindemann, et al., “Improving DES Coprocessor Throughput for Short Operations,” Proc. USENIX Security Symposium, 2001, 15 pages.
Office Action from U.S. Appl. No. 11/684,358 mailed Sep. 14, 2009.
Office Action from U.S. Appl. No. 11/684,358 mailed Mar. 25, 2010.
Abraham Santosh G.
Patel Sanjay
Sajjadian Farnad
Soun Sothea
Spracklen Lawrence A.
Merkel Lawrence J.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Oracle America Inc.
Thomas Shane M
LandOfFree
Low overhead access to shared on-chip hardware accelerator... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Low overhead access to shared on-chip hardware accelerator..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low overhead access to shared on-chip hardware accelerator... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4151547