Low latency message passing mechanism

Details Low latency message passing mechanism Low latency message passing mechanism

2005-09-26

2009-11-10

Portka, Gary J (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C709S212000, C711S121000

Reexamination Certificate

active

07617363

ABSTRACT:
In one embodiment, a method is provided. The method of this embodiment provides detecting by a network controller a flush occurring on a host bus of a DM (“direct messaging”) packet to a memory from a first cache line associated with a first processor; obtaining and storing the DM packet at a second cache line associated with the network controller; and sending the DM packet over a network to a third cache line associated with a second processor.

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International Search Report and Written Opinion, International Application No. PCT/US2006/037633, mailed Mar. 5, 2007, 11 pages.
International Preliminary Report on Patentability, International Application No. PCT/US2006/037633, mailed Apr. 3, 2008, 7 pages.
Office Action received for CN Patent Application No. 200680035108.8 mailed on Jun. 5, 2009, 7 pages and English translation of 14 pages.

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