Low latency request dispatcher

Details Low latency request dispatcher Low latency request dispatcher

2006-02-27

2010-10-12

Shah, Sanjiv (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Shared memory area

C711S138000

Reexamination Certificate

active

07814283

ABSTRACT:
A first-in-first-out (FIFO) queue optimized to reduce latency in dequeuing data items from the FIFO. In one implementation, a FIFO queue additionally includes buffers connected to the output of the FIFO queue and bypass logic. The buffers act as the final stages of the FIFO queue. The bypass logic causes input data items to bypass the FIFO and to go straight to the buffers when the buffers are able to receive data items and the FIFO queue is empty. In a second implementation, arbitration logic is coupled to the queue. The arbitration logic controls a multiplexer to output a predetermined number of data items from a number of final stages of the queue. In this second implementation, the arbitration logic gives higher priority to data items in later stages of the queue.

REFERENCES:
patent: 5517671 (1996-05-01), Parks et al.
patent: 5928354 (1999-07-01), Umeki et al.
patent: 6065088 (2000-05-01), Bronson et al.
Microsoft Computer Dictionary, Copyright 1999, Microsoft Press, Fourth Edition, p. 187.

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