Low latency synchronous memory performance switching using...

Details Low latency synchronous memory performance switching using... Low latency synchronous memory performance switching using...

2007-03-22

2011-11-08

Rojas, Midys (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S105000, C711S154000, C711S170000

Reexamination Certificate

active

08055871

ABSTRACT:
A synchronous memory device is configured to switch into and out of a full speed mode to change speed the speed of data transactions without significantly disturbing the frequency of a clock input to a PLL or DLL that provides the internal clock for the synchronous memory device. Since the PLL or DLL receives a clock signal whether or not the synchronous memory device is in a non-full speed mode, the PLL or DLL does not need to settle or relock when the clock signal is reapplied to exit a different speed mode and return to the full speed mode. Therefore, the latency incurred to switch into and out of different speed modes is reduced by eliminating or substantially reducing the time for settling or relocking the PLL or DLL.

REFERENCES:
patent: 6151664 (2000-11-01), Borkenhagen et al.
patent: 2002/0103962 (2002-08-01), Toda
patent: 2004/0172148 (2004-09-01), Horibe
patent: 2006/0233036 (2006-10-01), Blodgett et al.
Office Action, U.S. Appl. No. 11/690,006, dated Mar. 2, 2010.
Office Action, U.S. Appl. No. 11/690,007, dated Mar. 4, 2010.

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